DocumentCode :
1993522
Title :
VLSI architecture for a reconfigurable Spectrally Efficient FDM baseband transmitter
Author :
Whatmough, Paul N. ; Perrett, Marcus R. ; Isam, Safa ; Darwazeh, Izzat
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. Coll. London, London, UK
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
1688
Lastpage :
1691
Abstract :
Spectrally Efficient FDM (SEFDM) systems employ non-orthogonal overlapped carriers to improve spectral efficiency for future communication systems. One of the challenges for SEFDM systems is to demonstrate efficient hardware implementations for transmitters and receivers. This paper presents the first VLSI digital baseband transmitter architecture for SEFDM. The transmitter is reconfigurable between three bandwidth compression ratios, including OFDM and Fast OFDM, therefore supporting operation with current OFDM systems. Complexity analysis is presented of the proposed architecture, along with an area and power efficient hardware mapping, implemented using a 65nm CMOS cell library to provide analysis of area and power compared to a baseline OFDM transmitter.
Keywords :
CMOS logic circuits; OFDM modulation; VLSI; field programmable gate arrays; transmitters; CMOS cell library; FPGA; OFDM systems; OFDM transmitter; SEFDM systems; VLSI digital baseband transmitter architecture; bandwidth compression ratios; nonorthogonal overlapped carriers; power efficient hardware mapping; reconfigurable spectrally efficient FDM baseband transmitter; size 65 nm; Complexity theory; Frequency division multiplexing; OFDM; Power dissipation; Table lookup; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
ISSN :
0271-4302
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
Type :
conf
DOI :
10.1109/ISCAS.2011.5937906
Filename :
5937906
Link To Document :
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