High CMRR power efficient neural recording amplifier architecture

This work presents an architecture of neural recording amplifier based on a modified differential difference amplifier (DDA). The proposed circuit improves the performance with respect to capacitive feedback neural amplifiers and standard DDA based amplifiers by taking advantage of the high CMRR achievable in a DDA without jeopardizing the power consumption. In addition a novel technique for rejecting the DC component at the output of the amplifier and fixing the low cut-off frequency is described. The expected performance of the circuit is checked by Monte Carlo simulation, achieving 48dB gain in a 250Hz-8kHz bandwidth, with higher than 107dB CMRR (@5kHZ), 2.4μVrms input noise and 4.2 noise efficiency factor at a total current consumption of 16.5μA from a 3.3V power supply in a 0.5μm CMOS technology.