Title :
An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking
Author :
Pang, Yu ; Radecka, Katarzyna
Author_Institution :
Coll. of Photo-Electron., Chongqing Univ. of Posts & Telecommun., Chongqing, China
Abstract :
Allocating bit-widths is a necessary step in high-level synthesis. The main disadvantages of past methods, such as dynamic analysis or affine arithmetic, lie in low efficiency and coarse results which may lead to huge execution time and unnecessary additional bits for representation. In this paper, an algorithm is based on static analysis is proposed to perform range analysis and allocate integer bit-widths for an arithmetic datapath. The efficient algorithm can calculate the error bound between the exact range and the obtained range.
Keywords :
computability; fixed point arithmetic; network synthesis; SAT checking; arithmetic datapath; execution time; fixed-point arithmetic circuits; high-level synthesis; integer bit-width allocation; performing range analysis; static analysis; Algorithm design and analysis; Correlation; Delay; Engines; Polynomials; Upper bound;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937918