Embedded Low Complexity JPEG2000 Videocoding System

Author

Schuchter, A.

Author_Institution

Univ. of Salzburg Jakob, Salzburg

fYear

2007

fDate

4-5 Oct. 2007

Firstpage

77

Lastpage

82

Abstract

In this paper, we discuss an embedded hardware low complexity JPEG2000 video coding system. The hardware implementation is based on a software simulation system, where temporal redundancy is exploited by coding of differential frames which are arranged in an adaptive GOP structure. The hardware used mainly consists of a microprocessor (Analog Devices ADSP- BF533 Blackfin Processor) and a JPEG2000 chip (ADV202). DMAs (direct memory access) are introduced to optimize memory transfers in the system. It is shown that memory to memory DMAs lead to significant improvement in our proposed memory structure resulting in better performance.

Keywords

data compression; embedded systems; file organisation; microprocessor chips; video coding; DMA; adaptive GOP structure; direct memory access; embedded hardware low complexity JPEG2000 chip; microprocessor; software simulation system; videocoding system; Computational modeling; Embedded computing; Engines; Hardware; Microprocessors; Software systems; Telephony; Transform coding; Video coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded Systems for Real-Time Multimedia, 2007. ESTIMedia 2007. IEEE/ACM/IFIP Workshop on

Conference_Location

Salzburg

Print_ISBN

978-1-4244-1654-7

Type

conf

DOI

10.1109/ESTMED.2007.4375807

Filename

4375807