Title :
Some design issues in multi-chip FPGA implementation of DSP algorithms
Author :
Saha, Arindam ; Krishnamurthy, Rangasayee
Author_Institution :
Dept. of Electr. & Comput. Eng., Mississippi State Univ., MS, USA
Abstract :
Field programmable gate arrays (FPGAs) provide an innovative and flexible platform to implement and evaluate digital signal processing (DSP) applications. A CAD design methodology which is used to implement DSP algorithms is presented. An introduction is given to the various issues involved in the multi-chip partitioning of large DSP implementations, and approaches towards efficient auto-partitioners are also discussed in detail. The design and implementation of an 8-point 1D discrete cosine transform (DCT) and its inverse (IDCT) on a processor with FPGAs is presented in this paper, as an illustrative example of a typical DSP algorithm. The processor uses 16-bit precision, is implemented on six Xilinx 4000 type FPGAs and operates at 40 MHz
Keywords :
CAD; digital signal processing chips; discrete cosine transforms; electronic engineering computing; logic arrays; signal processing; 16-bit precision; 40 MHz; 8-point 1D discrete cosine transform; CAD; DSP algorithms; Xilinx 4000 family; auto-partitioners; design issues; digital signal processing applications; field programmable gate arrays; inverse discrete cosine transform; multi-chip FPGA implementation; multi-chip partitioning; Algorithm design and analysis; Computational modeling; Computer simulation; Design automation; Design methodology; Digital signal processing; Discrete cosine transforms; Field programmable gate arrays; Partitioning algorithms; Signal processing algorithms;
Conference_Titel :
Rapid System Prototyping, 1994. Shortening the Path from Specification to Prototype. Proceedings., Fifth International Workshop on
Conference_Location :
Grenoble
Print_ISBN :
0-8186-5885-1
DOI :
10.1109/IWRSP.1994.315902
