Title :
Compound synchronous reference frame PLL and unbalance control strategy for power conditioning system in weak grids
Author :
Liu, Baoqi ; Duan, Shanxu ; Liu, Bangyin ; Chen, Changsong ; Jiang, Xiaolong
Author_Institution :
Coll. of Electr. & Electron. Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China
Abstract :
An unbalanced control strategy is proposed to eliminate the 2nd harmonic at the DC bus, based on a compound synchronous reference frame phase-locked loop (CSRF-PLL) system, which composed of a T/4 delay positive sequence PLL (PS-PLL) and a T/3&T/6 delay negative sequence PLL (NS-PLL). The proposed PLL system can detect the phase angle and frequency of the utility voltage without errors, and both of the positive-sequence and negative-sequence components in dq-coordinate system can be figured out concurrently. By interaction between the original signal and the delayed one, effect of some characteristic harmonics, e.g. -5th and +7th harmonics, will be obliterated. According to the principle of simultaneous power balance, a negative sequence current is injected into the positive sequence reference current via a negative-sequence-to-positive-sequence transformation (NS-PST). And a regulator composed of a PI link parallel with 2nd and 6th quasi-resonant links is designed. Finally, the simulation and experimental results demonstrate that the proposed PLL system can work well even when the input signals have severe asymmetry in both amplitude and phase angle, its advantage at handling with harmonics is verified as well. Furthermore, the unbalanced control strategy can suppress the 2nd harmonic at the DC port evidently, which would reduce the power loss and lengthen the cycle-life of the batteries installed in the power conditioning system (PCS).
Keywords :
PI control; controllers; delays; harmonics suppression; phase locked loops; power system control; power system harmonics; smart power grids; DC bus; DC port; NS-PST; PI link; T/3 NS-PLL; T/3 delay negative sequence PLL; T/4 delay PS-PLL; T/4 delay positive sequence PLL; T/6 NS-PLL; T/6 delay negative sequence PLL; compound synchronous reference frame PLL system; dq-coordinate system; frequency detection; negative sequence current; negative-sequence components; negative-sequence-to-positive-sequence transformation; phase angle detection; phase locked loop system; positive sequence reference current; positive-sequence components; power conditioning system; power loss reduction; quasiresonant links; regulator; second harmonic elimination; simultaneous power balance principle; unbalance control strategy; utility voltage; weak grid system; Compounds; Delay; Harmonic analysis; Phase locked loops; Power harmonic filters; Regulators; Voltage control;
Conference_Titel :
Energy Conversion Congress and Exposition (ECCE), 2012 IEEE
Conference_Location :
Raleigh, NC
Print_ISBN :
978-1-4673-0802-1
Electronic_ISBN :
978-1-4673-0801-4
DOI :
10.1109/ECCE.2012.6342203