A self-biased PLL-tuned AER pixel for high-speed infrared imagers

This paper presents a novel digital pixel architecture for MWIR PbSe sensors and high-speed AER imagers. Low-power and compact circuits are proposed for pixel built-in log-domain temporal contrast, signal adapted self-biasing, linear current to spike frequency conversion under high-speed AER communications, and digital PLL-based technology and temperature compensated tuning. The proposed CMOS design techniques make extensive use of transistor subthreshold operation and circuit reuse. The resulting 40μm-pitch digital pixel is designed in standard 0.35μm 2P4M CMOS technology, and preliminary simulation results are reported.