Title :
Product families on-chip - combining the software product family paradigm with run-time reprogrammable hardware technology
Author_Institution :
Software Archit. Res. Group, VTT Electron., Oulu, Finland
Abstract :
Hardware and software can be co-designed as a single system to obtain high-performance computing solutions that use a minimum of resources such as CPU cycles and memory. Hardware/software co-design is often a complex and time consuming process. Software functionality is typically developed independently from hardware functionality and functional elements are not reused across similar products. Co-design is particularly important in system on-chip (SoC) development where an entire system consisting of both software and hardware is integrated on a single chip. Developing high-performance computing solutions in the form of SoCs in a repeatable manner is technically possible, but knowing how to apply software concepts in a hardware context and vice versa is still demanding at best. This paper summarizes the concepts and considerations that outline a case study that aims at combining the software product family paradigm with run-time reprogrammable hardware technology. The goal of the study is to define a formal framework for developing product families on-chip in a repeatable manner.
Keywords :
formal specification; hardware-software codesign; software architecture; system-on-chip; hardware-software co-design; high-performance computing; run-time reprogrammable hardware technology; software product family paradigm; system on-chip; Application software; Computer architecture; Costs; Field programmable gate arrays; Hardware; Runtime; Signal design; Software architecture; Software quality; System-on-a-chip;
Conference_Titel :
Computer Software and Applications Conference, 2005. COMPSAC 2005. 29th Annual International
Print_ISBN :
0-7695-2413-3
DOI :
10.1109/COMPSAC.2005.124