Title :
Design of LDPC coding schemes for exploitation of bit error rate diversity across dies in NAND flash memory
Author :
Motwani, Ravi ; Chong Ong
Author_Institution :
Intel Corp., USA
Abstract :
LDPC codes have been proposed for Flash memories due to their capability to correct higher number of bit errors. Several mechanisms can lead to bit errors in Flash memories. An extensive list of these mechanisms as enlisted in [1] includes program disturb from tunneling, quantum level noise effects, erratic tunneling, SILC-related data retention and read disturb, and detrapping-induced retention. Each of these effects can be modeled as a random event with its own statistical behavior. Due to the process uncertainties in the lithography, the above mechanisms vary from die to die leading to variability in the raw bit error rate (BER) for different dies of the Flash memory. This has an immense impact on design of error correction coding (ECC) schemes which combat the BER to achieve a specified uncorrectable bit error rate (UBER) target. If conventional ECC techniques are used, they have to be designed to handle the worst die BER, which is a big overkill. We propose a new LDPC coding scheme which exploits the BER diversity to its advantage and enables a system design for the average BER of the dies. The method is based on spreading the LDPC codeword over dies rather than packing a single LDPC codeword in one die. The system has to properly select the dies between which to split the LDPC codeword. The LDPC decoding has to be modified to account for the BER diversity. Simulations results show a large coding gain resulting from spreading a codeword, with minimal quality of service (QoS) impact. The improvement stems from the fact that the codeword splitting reduces the mean and the variance of the BER distribution. We also propose an LDPC code design which is customized to the codeword split across multiple dies. The proposed LDPC code design is on similar lines to its design for quasi-static fading channel. The LDPC code can be designed using density evolution to obtain an optimal degree distribution for a given BER distribution. Simulation results for the custom-designe- LDPC codes validate the hypothesis by showing appreciable coding gains.
Keywords :
NAND circuits; error correction codes; error statistics; fading channels; flash memories; lithography; parity check codes; quality of service; tunnelling; BER; ECC design; LDPC coding scheme design; LDPC decoding; NAND flash memory; QoS impact; SILC-related data retention; USER target; bit error rate; detrapping-induced retention; erratic tunneling; error correction coding design; lithography; quality of service; quantum level noise effect; quasi-static fading channel; statistical behavior; uncorrectable bit error rate; Bit error rate; Decoding; Encoding; Fading; Flash memories; Log-normal distribution; Parity check codes;
Conference_Titel :
Computing, Networking and Communications (ICNC), 2013 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-5287-1
Electronic_ISBN :
978-1-4673-5286-4
DOI :
10.1109/ICCNC.2013.6504218