A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications

Dataflow applications have proven to be well-suited for hardware implementation due to their intrinsic pipelined nature. Furthermore a wide range of algorithms, ranging from image analysis to map-reduce tasks, can be expressed using this paradigm. At the same time Field Programmable Gate Arrays (FPGA) start to be employed as hardware accelerators also in high-end systems coupled with General Purpose Processors (GPP). In this work we propose a programmable interconnection structure which permits to dynamically reconfigure the functionality of an FPGA implementing dataflow applications. A detailed analysis of the proposed solution shows that it is effectively able to increase the overall system flexibility helping in reducing the overall workload execution up to 25%, while at the same time reducing its variance.