Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter

This paper proposes a low-power, high-speed architecture of a reconfigurable root-raised cosine (RRC) filter which serves as a major component of a digital up converter (DUC). The proposed RRC filter can be reconfigured at any time to suit one of three different interpolation factors and one of two different roll-off factors pertaining to various modern wireless communication standards. The fact that the design is multiplexer-based has ensured reduction in power consumption. In addition, transposed direct form II realization of the RRC filter has enabled maximum operating frequency by placing a set of registers at proper locations of the data path. Power consumption of an FPGA implementation of the proposed filter has been found to be about 234 mW at 50 MHz clock frequency. However, the designed filter is capable of operating at a maximum clock frequency of 229 MHz on XC2VP30 FPGA devices while requiring only 7K gates. Significant reduction in area and power of the proposed RRC filter makes it very suitable for an area critical power efficient reconfigurable multi-standard DUC.