High voltage protection for USB transceivers in 45nm CMOS

Many present day IO specifications require over- voltage protection. USB2.0, a popular serial interface, requires a 5.25V short circuit protection for the signal pins. This becomes a challenging requirement to meet in Ultra Deep Sub-micron (UDSM) technologies. The challenge lies in protecting the low- voltage gate oxides from higher voltage in different modes of operation including power down. A protection circuit is proposed in this paper that also protects from overshoots due to a mismatched cable. The proposed circuit also ensures that supply for the output pad driver doesn´t get charged during the high voltage event. It continues to protect during power down drawing ~12μA current ensuring low power operation. The protection circuit presented in this paper is implemented in 45nm CMOS, without using any 3.3V gate-oxide transistors. This circuit consumes 300μA from 3.3V during functional mode. The area of this circuit is 90×320μm².