Controllable delay-insensitive processes and their reflection, interaction and factorisation

Delay-insensitive processes are typically implemented as asynchronous logic blocks; the possibility of transmission interference along the wires that connect them is considered to be a design error. Using DI-Algebra, the concepts of controllability, reflection, testing by interaction, and design by factorisation are explored. In general, a controllable process should be twice reflected so as to make it as abstract as possible.