Strained Si: Opportunities and challenges in nanoscale MOSFET

For the nanoscale MOSFET technology, the strain engineering is emerge as the most important performance booster technique in terms of carrier mobility, low scattering and consequently the high on current. In this paper, the state of art for nanoscale strained MOSFET has been reviewed in terms of performance improvement and manufacturability. Further, the strain engineering along with advanced performance booster technique/structure, raised Source/Drain (S/D), S/D extension engineering (underlap structure), High-K/Metal-gate, Extremely Thin Silicon On Insulator (ETSOI) and multigate device structure, have been studied to provide the guidelines for performance enhancement in nanoscale devices. In above cases, we will focus on reliability, advantages and probable solutions to the related issues. Although strain provide mobility enhancement for both NMOS and PMOS without alleviating leakage current but the use of strain Si in nanoscale MOSFET still create new challenges. The literature review has been extended to cover the various challenges of nanoscale strained MOSFET, scaling of strained MOSFET, mobility limitation in ballistic range and self-heating. The review signify that the strain engineering become the integral part of nanoscale MOSFET due to its various potential benefits without much fabrication overhead.