Title :
4-channel 35 Gbit/s parallel CMOS LDD
Author :
Yingmei Chen ; Jianwei Gong ; Jianguo Yao ; Ling Tian
Author_Institution :
Sch. of Inf. Sci. & Eng., Southeast Univ., Nanjing, China
Abstract :
The design of a 4-channel 35 Gbit/s parallel laser diode driver (LDD) using 65 nm CMOS technology is presented. The LDD driver consists of an input buffer stage, a pre-amplifier stage and an output driver stage. The three-stage cascaded amplifiers constitute the pre-amplifier stage, and an active feedback technique is employed to expand bandwidth without consuming a large area. The output driver stage introduces RC negative feedback and inductive shunt peaking techniques to broaden the bandwidth. Measurement results show that the operating rate of each channel is up to 35 Gbit/s and the power consumption per data rate is only 4.4 mW/(Gbit/s).
Keywords :
CMOS integrated circuits; circuit feedback; driver circuits; preamplifiers; semiconductor lasers; CMOS technology; RC negative feedback; active feedback technique; inductive shunt peaking techniques; input buffer stage; output driver stage; parallel laser diode driver; preamplifier stage; size 65 nm; three-stage cascaded amplifiers;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2015.0885
