An efficient hardware design of SIFT algorithm using fault tolerant reversible logic

Scale Invariant Feature Transform (SIFT) algorithm is used to generate image features which is very essential for object recognition, feature detection, image matching etc. This paper proposes an optimized hardware architecture for realizing the SIFT algorithm with reversible logic prototyped using Field Programmable Gate Array (FPGA). The digital hardware logic has been implemented with reversible and fault tolerant capabilities at significant design sections substituting the adder and multiplier functions which is one of the first of its kind of implementation of this application needed for designing energy efficient systems such as SoC (System on Chip) based robotic vision system. Reversible logic is emerging as an important research area for low power CMOS design, DSP applications and battery operated embedded systems meant for image processing. The reversible logic is implemented using our new proposed RFT (Reversible Fault Tolerant) gates (which is reversible as well as fault tolerant) that is used to design a new innovated adder circuit. The new adder circuit uses very less hardware resource which is again substituted with minimum complexity reversible gate. The proposed design shows invariancy to various image parameters such as scale, rotation, viewpoint and noise unlike other state of the art works. Moreover our design can process a frame of resolution 640*480 in 15 millisecond, at a rate of 64 frames per second which meets the real time video rate constraint, what represents a speed up of 415x compared to the software execution of the method.