Head-of-Line Blocking Avoidance in Networks-on-Chip

Many-core chip designs are the current manufacturing trend for high-performance computing. Different challenges lead to different designs, whether general purpose-driven chip multiprocessors (CMPs) or application-specific multiprocessor system-on-chips (MPSoCs) are deployed. An emerging problem is on-chip network congestion, due either to several traffic flows requesting the same resources (e.g. memory controllers) or to bursty traffic interfering with other flows. In this paper we propose BAHIA, which enables dynamic separation of bursty traffic from non-bursty one, thereby removing all the contention effects of bursts with a minimal impact on network overhead and with a marginal increase in area requirements. Results demonstrate a robust and effective splitting of traffic, so that non-bursty traffic achieves the desired low latencies even in bursty-prone conditions. By contrast, in our experiments, when BAHIA is not used, non-bursty traffic gets congested, latency increasing significantly and, in some cases, reaching a factor increase of 3x.