Highly linear current-controlled delay unit

A highly linear current-controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/output relation compared with an inversely proportional one in the traditional current-starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue-time-digital ADC is simulated using the proposed CCDU as a front-end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.