Efficient FPGA implementation of an adaptive noise canceller

Author

Stefano, Antonio Di ; Scaglione, Alessandro ; Giaconia, Costantino

Author_Institution

Dipt. di Ingegneria Elettrica, Palermo Univ., Italy

fYear

2005

fDate

4-6 July 2005

Firstpage

87

Lastpage

89

Abstract

A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.

Keywords

error analysis; field programmable gate arrays; interference suppression; least mean squares methods; signal denoising; ANC bandwidth; FPGA implementation; S/N ratio; adaptive noise canceller; hardware implementation; least mean square error algorithm; signal to noise ratio; Adaptive arrays; Bandwidth; Field programmable gate arrays; Hardware; Least squares approximation; Noise cancellation; Sensor arrays; Signal synthesis; Signal to noise ratio; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architecture for Machine Perception, 2005. CAMP 2005. Proceedings. Seventh International Workshop on

Print_ISBN

0-7695-2255-6

Type

conf

DOI

10.1109/CAMP.2005.22

Filename

1508169