A Compiler Analysis to Determine Useful Cache Size for Energy Efficiency

As processor and memory system speeds have significantly diverged, system designers have introduced ever larger caches in an effort to supply the processor with data at a rate it is capable of processing it. However, application characteristics vary and not all programs can effectively utilize large caches due to their inherent data reuse properties. The inability to use all the available cache capacity leads to wasted cache power dissipation. The rising specter of "dark silicon" makes it critical to avoid wasted power on a chip.In this paper, we develop a compile-time approach to analyze data reuse characteristics of affine computations and deduce the useful cache size(s) for a given system configuration. The non-useful cache can be power-gated to save power. Analysis of benchmarks shows that significant fractions of the last level cache of current processors may be turned off with no performance loss.