Built in self test for RAM using VHDL

Author

Husin, Mohd Heikal ; Leong, S.Y. ; Sabri, Mohd Faizul Mohd ; Nordiana, R.

Author_Institution

Fac. of Eng., Univ. Malaysia Sarawak, Kota Samarahan, Malaysia

fYear

2012

fDate

3-4 Dec. 2012

Firstpage

272

Lastpage

276

Abstract

This project emphasized mainly on software analysis. Modelsim-Altera 6.4a is the software that used to generate every single module of the Built-in-Self-Test (BIST) for Random access Memory (RAM) architecture. There are three key things to be concern in the BIST for RAM which is the Test Pattern Generator (TPG), Output Response Analysis (ORA) and RAM. The output of counter which is a type of TPG is analyzed to provide a pattern for March test algorithm. At the mean time, the ORA compare the output from decoder and the RAM output itself which modeled under the theory of numerical autonomy of error vectors from the circuit under test. The output of ORA, the comparator, will show pass or fail for faulty detection of RAM. The system has been successfully developed and vector waveform is used to examine the result of the system. From the result obtained, it showed that the system is working as expected with satisfactory result.

Keywords

automatic test pattern generation; built-in self test; fault diagnosis; hardware description languages; integrated circuit reliability; integrated circuit testing; numerical analysis; random-access storage; BIST; March test algorithm; Modelsim-Altera 6.4a software; ORA; RAM; RAM architecture; TPG; VHDL; built-in self test; circuit under test; decoder; error vectors; faulty detection; numerical autonomy theory; output response analysis; random access memory; software analysis; test pattern generator; BIST; ORA; RAM; TPG;

fLanguage

English

Publisher

ieee

Conference_Titel

Humanities, Science and Engineering (CHUSER), 2012 IEEE Colloquium on

Conference_Location

Kota Kinabalu

Print_ISBN

978-1-4673-4615-3

Type

conf

DOI

10.1109/CHUSER.2012.6504323

Filename

6504323