Hardware-efficient parallel FIR digital filter structures for symmetric convolutions

Based on fast FIR algorithms (FFA), this paper proposes new parallel finite-impulse response (FIR) filter structures, which are beneficial to symmetric convolutions in terms of the hardware cost. The proposed parallel FIR structures exploit the inherent nature of the symmetric coefficients reducing half the number of multipliers in subfilter section at the expense of additional adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh much less than multiplier in terms of silicon area, and besides the overhead from the additional adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a 3-parallel 72-tap filter, the proposed structure saves 24 multipliers at the expense of 7 adders, whereas for a 3-parallel 576-tap filter, the proposed structure saves 192 multipliers at the expense of 7 adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is large.