Multi-objective optimization of minority-3 functions for ultra-low voltage supplies

Low supply voltages, small currents and small circuit feature sizes will for CMOS logic typically coincide with deteriorating robustness, i.e. a reduction of a circuits ability to maintain correct functionality across all operating conditions. In this paper we examine three circuit topologies implementing the minority-3 function, operating at a power supply voltage of 150 mV in a standard 65 nm CMOS process. Using a heuristic multiobjective optimization algorithm we consider each circuits area and metrics for power and robustness, and optimize each circuit to find an approximation to the optimal trade-off surface (a Pareto front) for these objectives.