Energy efficient pseudo-cache architecture through fine-grained reconfigurability

Fueled by the exponential growth in transistors available to processor designers, cache memories became a very significant percentage of the overall area, power dissipation and energy consumption of modern systems. Instruction cache memories, however, typically hold highly redundant information in each of their columns, due to the repeated use of instructions and registers by compilers. Current memory architectures do not exploit this fact to reduce energy, consuming constant amounts of power regardless of switching activity. This work proposes the use of a fine-grained reconfigurable architecture to exploit this redundancy, providing an energy efficient on-chip storage element for embedded processors. The proposed architecture reached consumes up to 86% less energy, with an average reduction of 39%.