DocumentCode :
1996950
Title :
Evaluation of a distributed fault handler method for MPSoC
Author :
Hébert, Nicolas ; Almeida, Gabriel Marchesan ; Benoit, Pascal ; Sassatelli, Gilles ; Torres, Lionel
Author_Institution :
STMicroelectron., Crolles, France
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
2329
Lastpage :
2332
Abstract :
The increasing infant mortality and wear out failure rates observed in very deep sub micron silicon technologies is now a major problem for the design of future high-density SoCs. Emerging architectures based on Multi-Processor SoCs (MPSoCs) give the opportunity to exploit the natural redundancy to control the system performance in presence of failures. In this paper we evaluate the impact of a distributed fault-handler strategy on the system in term of cost and feasibility. We also discuss strategies for applying this technique to a distributed MPSoC architecture.
Keywords :
fault tolerance; multiprocessing systems; parallel architectures; redundancy; system-on-chip; MPSoC; distributed fault handler method; multiprocessor architecture; natural redundancy; Arrays; Computer crashes; Hardware; Registers; Silicon; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
ISSN :
0271-4302
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
Type :
conf
DOI :
10.1109/ISCAS.2011.5938069
Filename :
5938069
Link To Document :
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