DocumentCode
1997042
Title
System design and verification process for LHC programmable trigger electronics
Author
Crosetto, Dario B.
Volume
1
fYear
1999
fDate
1999
Firstpage
279
Abstract
The rapid evolution of electronics has made it essential to design systems in a technology-independent form that will permit their realization in any future technology. This article describes two practical projects that have been developed for fast, programmable, scalable, modular electronics for the first-level trigger of Large Hadron Collider (LHC) experiments at CERN, Geneva. In both projects, one for the front-end electronics and the second for executing first-level trigger algorithms, the whole system requirements were constrained to two types of replicated components. The overall problem is described, the 3D-Flow design is introduced as a novel solution, and current solutions to the problem are described and compared with the 3D-Flow solution. The design/verification methodology proposed allows the user´s real-time system algorithm to be verified down to the gate-level simulation on a technology-independent platform, thus yielding the design for a system that can be implemented with any technology at any time
Keywords
circuit CAD; formal verification; logic testing; nuclear electronics; trigger circuits; LHC programmable trigger electronics; Large Hadron Collider; design/verification methodology; first-level trigger; first-level trigger algorithms; front-end electronics; gate-level simulation; modular electronics; real-time system algorithm; system design; verification process; Algorithm design and analysis; Application software; Backplanes; Hardware; Large Hadron Collider; Microprocessors; Pipeline processing; Real time systems; Scalability; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium, 1999. Conference Record. 1999 IEEE
Conference_Location
Seattle, WA
ISSN
1082-3654
Print_ISBN
0-7803-5696-9
Type
conf
DOI
10.1109/NSSMIC.1999.842493
Filename
842493
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