Dependability Assessment for the Selection of Embedded Cores

Many designers bet on reducing time-to-market costs by integrating off-the-shelf (OTS) cores in their embedded solutions, while looking after maintaining the confidence placed by users in their products. Balancing these aspects is challenging and claims for suitable techniques to select, among eligible candidates, those exhibiting adequate levels of dependability. Thus, the early and efficient dependability assessment of embedded cores is nowadays a major and complex challenge. This paper focuses on the assessment and comparison of dependability attributes evinced by hardware OTS cores. It proposes the use of field programmable gate arrays to emulate the cores behaviour under different execution profiles (workloads and faultloads). Three cores devoted to signal filtering purposes are considered as a case study. Results show not only the feasibility of this approach but also the kind of selection process supported by the proposed technique.