DocumentCode
1997399
Title
[Cover art]
fYear
2008
fDate
25-29 May 2008
Abstract
The following topics are dealt with: SoC infrastructure; RF testing; safe test generation; design validation; memory testing; delay faults; circuit simulation; IC test generation; DFT; SoC testing; mixed-signal devices; IC yield enhancement; online testing and soft error mitigation.
Keywords
circuit simulation; integrated circuit testing; integrated circuit yield; mixed analogue-digital integrated circuits; radiation hardening (electronics); radiofrequency integrated circuits; system-on-chip; DFT; IC yield enhancement; RF testing; SoC infrastructure; circuit simulation; delay faults; design validation; memory testing; mixed-signal devices; online testing; safe test generation; soft error mitigation;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2008 13th European
Conference_Location
Verbania
Print_ISBN
978-0-7695-3150-2
Type
conf
DOI
10.1109/ETS.2008.43
Filename
4556008
Link To Document