Two-way balance-tolerant partitioning based on fuzzy graph clustering for hierarchical design of VLSI systems

In this paper, first, we model a two-way balance-tolerant partitioning for a VLSI circuit. Furthermore, we propose an efficient approach based on one kind of fuzzy graph clustering, probabilistic graph clustering, to obtain a two-way balance-tolerant partitioning of VLSI circuits. In this approach, a circuit netlist is represented as an edge-weighted undirected graph by transforming a hypergraph with a clique net model. Furthermore, probabilistic memberships of the vertices in the graph will be obtained by probabilistic graph clustering, respectively. Finally, according to these probabilistic memberships, the graph will be separated into two balanced sub-graphs with a tolerant size constraint. In contrast, a VLSI circuit will be partitioned into two balance-tolerant sub-circuits. The proposed approach based on probabilistic graph clustering is implemented to obtain two balance-tolerant sub-circuits on some industry circuit benchmarks. As a result, the experimental results show that the proposed two-way balance-tolerant partitioning is effective for hierarchical design of VLSI circuits