Title :
Secure transmission of gate level description
Author :
Ghosal, Sandip ; Mitra, Debasis
Author_Institution :
Dept. of Inf. Technol., Nat. Inst. of Technol., Durgapur, India
Abstract :
Modern system-on-chip (SoC) design cycle strongly depends on secure exchange of intellectual properties (IPs) between core-authors, integrators, foundries etc. However the sharing of IP between authorities involves high security risks in today´s competitive market. Since IP usually involves large amount of data, conventional message encryption techniques needs improvised use in this case. In this paper we have proposed a technique for secure transmission of the gate level description of a combinational circuit over public network. An easy to implement and computationally inexpensive encryption technique is used to encrypt the description. It enables intended receiver to decrypt the description using owner´s certificate. It also facilitates in identifying any intentional modification in the description made by any unauthorized party. Experimental results show that the proposed technique can withstand variety of attacks from intruders.
Keywords :
combinational circuits; cryptography; industrial property; integrated circuit design; system-on-chip; IP sharing; combinational circuit; description encryption; gate level description; owner certificate; public network; secure intellectual property exchange; secure transmission; security risks; system-on-chip design cycle; unauthorized party; Encryption; Libraries; Logic gates; Receivers; Vectors; Watermarking;
Conference_Titel :
Recent Advances in Information Technology (RAIT), 2012 1st International Conference on
Conference_Location :
Dhanbad
Print_ISBN :
978-1-4577-0694-3
DOI :
10.1109/RAIT.2012.6194498