A 0.13µm CMOS 1.5-to-2.15GHz low power transmitter front-end for SDR applications

A 0.13 um CMOS 1.5-to-2.15 GHz low power transmitter front-end with direct quadrature voltage modulation for SDR applications is presented. The SDR transmitter front-end consists of PGA, passive RC filter, direct quadrature voltage modulator, 25%-duty-cycle LO generator and programmable PA-Driver with reconfigurable operation frequency bands. An on-chip transformer with switched- capacitor array provides the wide-band reconfigurable frequency band covering and differential-to-single-ended conversion. The passive voltage mixer with 25%-duty-cycle LO implements the frequency up-conversion with low noise and low conversion loss. The SDR transmitter front-end has been implemented in 0.13 um CMOS, the measured results show that this front-end could provide 22 dB gain with a step of 2dB and output higher than OdBm power across 1.5-to-2.15 GHz frequency range with a maximum power consumption of 42 mW. The die area is 1.6 mm* 1.2 mm.