Title :
Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation
Author :
Jenihhin, Maksim ; Raik, Jaan ; Chepurov, Anton ; Ubar, Raimund
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn
Abstract :
The paper proposes a novel method for PSL language assertions simulation-based checking. The method uses a system representation model called High-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in PSL. Other contributions of the paper are methodology for direct conversion of PSL properties to HLDD and HLDD-based simulator modification for assertions checking support. Experimental results show the feasibility and efficiency of the proposed approach.
Keywords :
electronic engineering computing; hardware description languages; logic design; PSL language assertions; high-level decision diagrams; property specification language; simulation based checking; temporally extended high-level decision diagram; Application software; Computational modeling; Computer simulation; Concurrent computing; Design automation; Emulation; Hardware; Paper technology; Specification languages; Testing; Property Specification Language; assertion checking; decision diagrams;
Conference_Titel :
Test Symposium, 2008 13th European
Conference_Location :
Verbania
Print_ISBN :
978-0-7695-3150-2
DOI :
10.1109/ETS.2008.22