Title :
Implementation of double arbiter PUF and its performance evaluation on FPGA
Author :
Machida, Takanori ; Yamamoto, Dai ; Iwamoto, Mitsugu ; Sakiyama, Kazuo
Author_Institution :
Univ. of Electro-Commun., Chofu, Japan
Abstract :
Low uniqueness and vulnerability to machine-learning attacks are known as two major problems of Arbiter-Based Physically Unclonable Function (APUF) implemented on FPGAs. In this paper, we implement Double APUF (DAPUF) that duplicates the original APUF in order to overcome the problems. From the experimental results on Xilinx Virtex-5, we show that the uniqueness of DAPUF becomes almost ideal, and the prediction rate of the machine-learning attack decreases from 86% to 57%.
Keywords :
field programmable gate arrays; learning (artificial intelligence); FPGA; Xilinx Virtex-5; arbiter-based physically unclonable function; field programmable gate arrays; machine-learning attacks; Delays; Field programmable gate arrays; Resistance; Support vector machines; Wires; Wiring;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
978-1-4799-7790-1
DOI :
10.1109/ASPDAC.2015.7058919
