DocumentCode
1997843
Title
A negative-resistance sense amplifier for low-voltage operating STT-MRAM
Author
Umeki, Yohei ; Yanagida, Koji ; Yoshimoto, Shusuke ; Izumi, Shintaro ; Yoshimoto, Masahiko ; Kawaguchi, Hiroshi ; Tsunoda, Koji ; Sugii, Toshihiro
Author_Institution
Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan
fYear
2015
fDate
19-22 Jan. 2015
Firstpage
8
Lastpage
9
Abstract
This paper exhibits a 65-NM 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at 0.38V. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 1.70 μW at that voltage.
Keywords
MOSFET; MRAM devices; amplifiers; low-power electronics; negative resistance circuits; boosted-gate nMOS; frequency 0.526 MHz; low-voltage operating STT-MRAM; magnetoresistance random access memory; memory size 8 MByte; negative-resistance pMOS; negative-resistance sense amplifier; power 1.70 muW; size 65 nm; spin transfer torque; time 1.9 mus; voltage 0.38 V; Charge pumps; Clamps; Educational institutions; IP networks; Logic gates; Magnetic tunneling; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location
Chiba
Print_ISBN
978-1-4799-7790-1
Type
conf
DOI
10.1109/ASPDAC.2015.7058920
Filename
7058920
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