Title :
A novel self-aligned gate-overlapped LDD poly-Si TFT with high reliability and performance
Author :
Hatano, M. ; Akimoto, H. ; Sakai, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
Gate-overlapped LDD poly-Si TFT fabricated by using poly Si-sidewall gates self-alignment process (Sa-GOLD), is proposed. The Sa-GOLD TFTs are suitable for high-speed operation because of small overlapping capacitance and large transconductance. Furthermore, they can reduce the drain electric field, and provide high reliability against drain-avalanche hot-carrier.
Keywords :
capacitance; elemental semiconductors; hot carriers; semiconductor device reliability; silicon; thin film transistors; Sa-GOLD; Si; drain electric field; drain-avalanche hot-carrier; high-speed operation; overlapping capacitance; polysilicon-sidewall gates self-alignment process; reliability; self-aligned gate-overlapped LDD polysilicon TFT; transconductance; Anisotropic magnetoresistance; Gold; Hot carriers; Integrated circuit reliability; Laboratories; Leakage current; Parasitic capacitance; Reliability engineering; Thin film transistors; Transconductance;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.650438
