DocumentCode :
1997909
Title :
Detection and correction of soft errors in memory system
Author :
Ramya, M. ; Preethi, S.
Author_Institution :
Kalaignar Karunanidhi Inst. of Technol., Coimbatore, India
fYear :
2013
fDate :
19-21 Dec. 2013
Firstpage :
1
Lastpage :
6
Abstract :
Nowadays, The memory applications are more concerned with single event upsets. They invert the stored logic values in flip flop and memory cells. This issue is more serious when the affected memory cells are part of the configuration memory used for programming the circuit functionality. The occurrence of error can be corrected by reprogramming, which is caused due the alteration of circuit functionality. Here we have compared two decoders of error correction codes for issues in the programming circuits. A Hamming Decoder and a One-Step Majority Logic Decoder (OS-MLD) for the Difference-Set Cyclic Codes (DSCC) are analyzed yielding surprisingly unexpected results for their SEU susceptibility, which are interesting for application designers.
Keywords :
Hamming codes; error correction codes; flip-flops; majority logic; memory architecture; DSCC; Hamming decoder; OS-MLD; circuit functionality programming; decoders; difference-set cyclic codes; error correction codes; flip flop; memory cells; memory system; one-step majority logic decoder; soft error correction; soft error detection; stored logic values; Complexity theory; Decoding; Equations; Error correction codes; Mathematical model; Parity check codes; Random access memory; DSCC; Single event upsets; one step Majority Logic Decoder;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Computing and Communication Systems (ICACCS), 2013 International Conference on
Conference_Location :
Coimbatore
Type :
conf
DOI :
10.1109/ICACCS.2013.6938723
Filename :
6938723
Link To Document :
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