Title :
A 128-way FPGA platform for the acceleration of KLMS algorithm
Author :
Xiaowei Ren ; Yu Qihang ; Badong Chen ; Nanning Zheng ; Pengju Ren
Author_Institution :
Inst. of Artificial Intell. & Robot., Xi´an Jiaotong Univ., Xi´an, China
Abstract :
This paper proposes a 128-way parallel FPGA platform to accelerate the kernel least mean square (KLMS) algorithm. With the adoption of a quantized method and pipeline technology, this platform which works at 200MHz is 4827 times faster, on average, than the Matlab code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.
Keywords :
field programmable gate arrays; least mean squares methods; microprocessor chips; quantisation (signal); FPGA; Intel Core i5-2320 CPU; Matlab code; field programmable gate arrays; frequency 200 MHz; frequency 3 GHz; kernel least mean square algorithm; pipeline technology; quantized method; Field programmable gate arrays; Hardware; Kernel; MATLAB; Pipelines; Signal processing; Signal processing algorithms;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
978-1-4799-7790-1
DOI :
10.1109/ASPDAC.2015.7058925
