Design of a scalable many-core processor for embedded applications

Author

Hsiao-Wei Chien ; Jyun-Long Lai ; Chao-Chieh Wu ; Chih-Tsun Huang ; Ting-Shuo Hsu ; Jing-Jia Liou

Author_Institution

Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2015

fDate

19-22 Jan. 2015

Firstpage

24

Lastpage

25

Abstract

We present a novel design of scalable many-core processor with its comprehensive development framework, including the Electronic System Level, Register Transfer Level, and full-system prototyping platforms. Architecture exploration, performance evaluation and system verification/validation can be done across different abstraction levels. With our hardware-independent software layer, applications built on top of the fast virtual platform can be executed seamlessly on the prototype. The emulation result justifies the effectiveness of our processor architecture in embedded applications.

Keywords

embedded systems; integrated circuit design; microprocessor chips; multiprocessing systems; parallel architectures; performance evaluation; abstraction levels; architecture exploration; development framework; electronic system level; embedded applications; full-system prototyping platforms; hardware-independent software layer; microprocessor design; performance evaluation; processor architecture; register transfer level; scalable many-core processor design; system validation; system verification; virtual platform; Computer architecture; Emulation; Graphics; Hardware; Software; System-on-chip; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

978-1-4799-7790-1

Type

conf

DOI

10.1109/ASPDAC.2015.7058928

Filename

7058928