DocumentCode :
1998115
Title :
Analysis of threshold voltage shift caused by bias stress in low temperature poly-Si TFTs
Author :
Inoue, S. ; Ohshima, H. ; Shimoda, T.
Author_Institution :
Seiko Epson Corp., Nagano, Japan
fYear :
1997
fDate :
10-10 Dec. 1997
Firstpage :
527
Lastpage :
530
Abstract :
The degradation phenomenon of low temperature (/spl les/425/spl deg/C) polycrystalline-silicon thin film transistors (poly-Si TFTs) caused by self-heating has been investigated. In n-channel TFTs, the subthreshold characteristics are significantly and rapidly shifted in the positive direction. This is particularly marked in wide channel TFTs and/or small size TFTs. In order to improve reliability, TFTs with divided channel patterns have also been introduced.
Keywords :
elemental semiconductors; semiconductor device reliability; silicon; thin film transistors; 300 to 425 degC; Si; bias stress; degradation phenomenon; divided channel patterns; low temperature polysilicon TFTs; n-channel TFTs; reliability; self-heating; small size TFTs; subthreshold characteristics; threshold voltage shift; wide channel TFTs; Artificial intelligence; Degradation; Electrodes; Glass; Open wireless architecture; Substrates; Temperature; Thermal stresses; Thin film transistors; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-4100-7
Type :
conf
DOI :
10.1109/IEDM.1997.650439
Filename :
650439
Link To Document :
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