A hybrid phase-locked loop for CDR Applications

In this paper, a hybrid phase and frequency detector (PFD) for phase-locked loop (PLL) based clock and data recovery (CDR) applications is presented. The PFD starts the phase detection process in a binary mode, for a faster acquisition time and a higher pull in range, and after the binary PLL locks, the PD switches to the linear mode of operation resulting in a lower output jitter. The frequency acquisition range of the presented PFD is significant and it virtually can handle any data frequency. The data frequency can however be as high as the clock frequency. In all simulations of the PLL, the pull-in range of the PLL is limited by the tuning range of the voltage-controlled oscillator (VCO). A prototype PLL is designed in a 0.13 μm CMOS technology and has a lock range from 8.3 to 9.6 GHz, peak-to-peak jitter of 0.1 UI, and a worst-case lock time of 30 ns. The PLL consumes 36 mW from a 1.2 V supply.