Title :
A NoC Emulation/Verification Framework
Author :
Liu, Peng ; Xiang, Chunchang ; Wang, Xiaohang ; Xia, Binjie ; Liu, Yangfan ; Wang, Weidong ; Yao, Qingdong
Author_Institution :
Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou
Abstract :
The emulation and functional validation are essential to assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection networks architecture. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy, and decrease usage of the resource of field programmable gate array.
Keywords :
field programmable gate arrays; instruction sets; multiprocessor interconnection networks; network-on-chip; performance evaluation; field programmable gate array; flexible hardware/software networks-on-chip open platform emulation framework; functional validation; instruction set simulator; on-chip interconnection networks architecture; universal serial bus communicator control; Computational modeling; Computer aided instruction; Computer architecture; Computer simulation; Emulation; Field programmable gate arrays; Hardware; Network-on-a-chip; Prototypes; Universal Serial Bus; FPGA; emulation; multiprocessor systems-on-chip (MPSoC); networks-on-chip (NoC);
Conference_Titel :
Information Technology: New Generations, 2009. ITNG '09. Sixth International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-3770-2
Electronic_ISBN :
978-0-7695-3596-8
DOI :
10.1109/ITNG.2009.197
