Scheduling Techniques for Multi-Core Architectures

In this paper we propose a template of architectures that comprise of multiple autonomous processors interconnected via FIFO links. We extend conventional list scheduling algorithm to schedule applications on the proposed distributed architecture template. We explain how a graph representation of an architecture can be used to route operands and how edge weights are assigned to find the shortest legal path an operand can take. We also propose a technique to shorten the path an operand takes by exploiting the copies of the operand distributed over the architecture. Finally, we show the effectiveness of the proposed techniques in reducing execution times of selected benchmarks.