A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection

Author

Siriburanon, Teerachot ; Ueno, Tomohiro ; Kimura, Kento ; Kondo, Satoshi ; Wei Deng ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2015

fDate

19-22 Jan. 2015

Firstpage

42

Lastpage

43

Abstract

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.

Keywords

CMOS integrated circuits; field effect MIMIC; injection locked oscillators; low-power electronics; millimetre wave oscillators; phase locked loops; phase noise; CMOS implementation; QILO; SS-PLL; frequency 20 GHz; frequency 58.3 GHz to 65.4 GHz; in-band phase noise; low noise PLL; low power sub-harmonically injection-locked PLL; out-of-band phase noise; phase locked loops; power 14 mW; power 20.2 mW; power 34.2 mW; quadrature injection locked oscillator; size 65 nm; sub-harmonic injection techniques; sub-sampling PLL; sub-sampling phase detection; CMOS integrated circuits; Clocks; Frequency synthesizers; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

978-1-4799-7790-1

Type

conf

DOI

10.1109/ASPDAC.2015.7058977

Filename

7058977