All-digital PLL array provides reliable distributed clock for SOCs

Author

Javidan, M. ; Zianbetov, E. ; Anceau, F. ; Galayko, D. ; Korniienko, A. ; Colinet, E. ; Scorletti, G. ; Akré, J.M. ; Juillard, J.

Author_Institution

LIP6 Lab., UPMC Sorbonne Univ., Paris, France

fYear

2011

fDate

15-18 May 2011

Firstpage

2589

Lastpage

2592

Abstract

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.

Keywords

CMOS digital integrated circuits; VLSI; clocks; digital phase locked loops; integrated circuit reliability; system-on-chip; CMOS technology; SOC; VLSI implementation; all-digital PLL array; clock distribution; clock generation; distributed clock reliability; globally synchronous locally synchronous chip; high-order bidirectional PLL network; size 65 nm; Clocks; Oscillators; Phase frequency detector; Phase locked loops; Simulation; Stability analysis; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5938134

Filename

5938134