Title :
Low power DCT architecture for image compression
Author :
Vaithiyanathan, D. ; Seshasayanan, R.
Author_Institution :
Dept. of Electron. & Commun. Eng., Anna Univ., Chennai, India
Abstract :
In this paper, we have proposed an efficient approximation for the 8-point discrete cosine transform (DCT). The proposed 8×8 transformation matrix contains only zeros and ones which requires only adders, thus avoiding the need for multiplication and bit shift operations. The new class transform requires only 16 additions, which highly reduces the computation complexity with negligible degradation in peak signal to noise ratio (PSNR). We evaluate the performance of the proposed designs in terms of area, speed and power consumption in TSMC 180nm complementary metal-oxide-semiconductor (CMOS) technology. The analysis obtained from the implementation shows that the proposed algorithm is superior to the existing approximation techniques with 25.39% reduction in power and 15.43% area optimization.
Keywords :
CMOS integrated circuits; adders; approximation theory; data compression; discrete cosine transforms; image coding; matrix algebra; power aware computing; power consumption; 8-point discrete cosine transform; CMOS technology; PSNR; TSMC; adders; bit shift operations; complementary metal-oxide-semiconductor technology; computation complexity; image compression; low power DCT architecture; peak signal to noise ratio; power consumption; size 180 nm; transformation matrix; Approximation methods; Complexity theory; Computer architecture; Discrete cosine transforms; Image coding; PSNR; DCT approximation; Multiplication free transform; VLSI architecture; image compression; low complexity;
Conference_Titel :
Advanced Computing and Communication Systems (ICACCS), 2013 International Conference on
Conference_Location :
Coimbatore
DOI :
10.1109/ICACCS.2013.6938745