Title :
The STAR DAQ receiver board
Author :
LeVine, M.J. ; Ljubicic, A., Jr. ; Schulz, M.W. ; Scheetz, R. ; Consiglio, C. ; Padrazo, D. ; Zhao, Y.
Author_Institution :
Brookhaven Nat. Lab., Upton, NY, USA
Abstract :
Data digitized on the STAR TPC detector are transmitted via 1.5 Gbit/sec optical fiber to the DAQ receiver boards (RE) located in Sector VME crates. The RE contains the optical receiver, G-link decoder, high speed bus to deliver data to three Mezzanines, which perform the processing. The RE back end provides an interface between VF/IE64 and PCI, serving as interconnect between all of the Mezzanines, the VME bus, and resources local to the receiver board. Each Mezzanine hosts an Intel i960HD superscalar RISC CPU, which performs 2-dimensional cluster-finding and data formatting. Dual-ported VRAM provide storage for 12 TPC events. Incoming data are processed in real time by a bank of ASICs which perform pedestal subtraction, 10-bit to 8-bit compression via table lookup, and compilation of a sequence pointer bank for use by the CPU during cluster-finding. Communication among the i960s and the master CPU in the VME crate takes place through mailboxes and doorbells implemented in the i960-PCI bridge chips
Keywords :
application specific integrated circuits; data acquisition; decoding; optical receivers; reduced instruction set computing; table lookup; 1.5 Gbit/sec optical fiber; 2-dimensional cluster-finding; ASICs; G-link decoder; Intel i960HD superscalar RISC CPU; PCI; STAR DAQ receiver board; STAR TPC detector; Sector VME crates; VF/IE64; data formatting; doorbells; dual-ported VRAM; high speed bus; mailboxes; optical receiver; table lookup; Amplitude shift keying; Connectors; Data acquisition; Decoding; Detectors; Laboratories; Optical fibers; Optical receivers; Reduced instruction set computing; SDRAM;
Conference_Titel :
Real Time Conference, 1999. Santa Fe 1999. 11th IEEE NPSS
Conference_Location :
Sante Fe, NM
Print_ISBN :
0-7803-5463-X
DOI :
10.1109/RTCON.1999.842573