Compiler-Based Data Prefetching and Streaming Non-temporal Store Generation for the Intel(R) Xeon Phi(TM) Coprocessor

Author

Krishnaiyer, Rakesh ; Kultursay, Emre ; Chawla, Pallvi ; Preis, Sebastian ; Zvezdin, Anatoly ; Saito, Hiroshi

fYear

2013

fDate

20-24 May 2013

Firstpage

1575

Lastpage

1586

Abstract

The Intel® Xeon Phi™ coprocessor has software prefetching instructions to hide memory latencies and special store instructions to save bandwidth on streaming non-temporal store operations. In this work, we provide details on compiler-based generation of these instructions and evaluate their impact on the performance of the Intel® Xeon Phi™ coprocessor using a wide range of parallel applications with different characteristics. Our results show that the Intel® Composer XE 2013 compiler can make effective use of these mechanisms to achieve significant performance improvements.

Keywords

coprocessors; parallel processing; performance evaluation; program compilers; storage management; Intel Composer XE 2013 compiler; Intel Xeon Phi coprocessor; bandwidth saving; compiler-based instruction generation; compiler-based software prefetching instructions; memory latencies; nontemporal store generation operation streaming; parallel applications; performance evaluation; Bandwidth; Coprocessors; Hardware; Prefetching; Vectors; Intel Xeon Phi; compiler; coprocessor; non-temporal store; performance; prefetching;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International

Conference_Location

Cambridge, MA

Print_ISBN

978-0-7695-4979-8

Type

conf

DOI

10.1109/IPDPSW.2013.231

Filename

6651054