Modeling and CAD of an Ultra-Broadband Monolithic 5-bit Digital Attenuator

The modeling techniques, computer-aided design (CAD) approach, and measured performance of an ultra-broadband (DC-14 GHz) monolithic 5-bit digital attenuator are presented. The two attenuator chips, with total dimensions of 1.3 × 2.7 mm, consume no DC power and provide 15.5 dB of dynamic range with 0.5-dB step resolution and excellent phase tracking. The design is based on passive field-effect transistor (FET) parameters derived from a dual-energy ion-implantation profile and FET geometries. The FET equivalent circuit element values are modeled as a function of recess depth for process monitoring and control. Good agreement is obtained between measured and modeled results.