• DocumentCode
    1998846
  • Title

    Formal verification of a commercial serial bus interface

  • Author

    Plessier, Bernard ; Pixley, Carl

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1995
  • fDate
    28-31 Mar 1995
  • Firstpage
    378
  • Lastpage
    382
  • Abstract
    A new technique for the analysis of sequential hardware designs is illustrated on a serial bus interface. A set of experiments using models of the bus interface and temporal logic formulae is discussed
  • Keywords
    formal verification; logic testing; sequential circuits; system buses; temporal logic; bus interface; formal verification; sequential hardware designs; serial bus interface; temporal logic; Data structures; Emulation; Formal verification; Hardware; Logic; Mathematical model; Microprocessors; Protocols; Registers; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computers and Communications, 1995., Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix Conference on
  • Conference_Location
    Scottsdale, AZ
  • Print_ISBN
    0-7803-2492-7
  • Type

    conf

  • DOI
    10.1109/PCCC.1995.472465
  • Filename
    472465
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1998846