Title :
Formal verification of a commercial serial bus interface
Author :
Plessier, Bernard ; Pixley, Carl
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
A new technique for the analysis of sequential hardware designs is illustrated on a serial bus interface. A set of experiments using models of the bus interface and temporal logic formulae is discussed
Keywords :
formal verification; logic testing; sequential circuits; system buses; temporal logic; bus interface; formal verification; sequential hardware designs; serial bus interface; temporal logic; Data structures; Emulation; Formal verification; Hardware; Logic; Mathematical model; Microprocessors; Protocols; Registers; Testing;
Conference_Titel :
Computers and Communications, 1995., Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-2492-7
DOI :
10.1109/PCCC.1995.472465
