An expandable current-mode ADC with power optimization technique

A low delay and speed efficient current mode Analog to Digital Converter has been described. The Analog to digital converter architecture generates 4-bit digital output in two stages. Different current comparator architectures have been used in the design and for each, the effect on the speed and area of the Analog to digital converter has been determined. Further, a power optimization technique has been suggested to reduce dynamic power dissipation in the ADC. It has been designed using 0.18 μm CMOS technology and simulation results have been obtained using PSpice.